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DFT Engineers
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Vegazva Group
Santa Clara, CA (In Person)
Full-Time
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Job Description
Header Overview Join our innovative team as a DFT (Design for Test) Engineer and play a pivotal role in enhancing the manufacturability and testability of complex electronic systems. In this dynamic position, you will collaborate closely with design, manufacturing, and quality assurance teams to develop robust testing methodologies that ensure high-quality, reliable products. Your expertise will help streamline production processes, reduce time-to-market, and improve overall product performance. This role offers an exciting opportunity to work at the forefront of electronic design and testing, contributing to cutting-edge projects across diverse technological domains. Responsibilities Develop and implement DFT strategies for FPGA, SoC (System on Chip), and PCB designs to facilitate efficient testing and debugging. Design test patterns, scan chains, and boundary scan architectures using SystemVerilog, MATLAB, and scripting languages like Python or Perl. Conduct root cause analysis on test failures or manufacturing defects to identify underlying issues in electrical systems or signal processing pathways. Collaborate with design engineers to integrate test features into schematics and system design documentation utilizing AutoCAD, Revit, Revit, MicroStation, or SolidWorks. Support manufacturing by creating detailed project schedules for testing phases and coordinating with production teams to ensure timely execution. Perform debugging of firmware and hardware components using tools such as oscilloscopes, ohmmeters, soldering equipment, and vision inspection systems. Contribute to continuous improvement initiatives by analyzing test data, optimizing test coverage, and enhancing test automation processes. Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals Experience with industry standard