Senior Manager - Design Engineering (IP)

Senior Manager - Design Engineering (IP) Microchip Technology Inc United States, California, Roseville 101 Creekside Ridge Court (Show on map) May 12, 2026 Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

As an IP Manager in the Microchip Data Center Solutions group, you will be responsible for the strategic sourcing, acquisition, and management of intellectual property services and assets from internal and external IP vendors. This role ensures seamless coordination between internal Program/I2R teams and IP vendors, manages service agreements and budgets, and facilitates the timely and cost-effective procurement of IP protection in alignment with the company's business objectives.

Key Responsibilities:

IP Procurement:

Own the end-to-end procurement process for third-party IPs used in data center SoC programs. Maintain an IP roadmap aligned with program planning, technology evolution, and product strategy. Evaluate IP solutions based on technical, quality, performance, security, and long-term support criteria.

Vendor Management & Contract Negotiation:

Serve as the primary point of contact for all IP vendors throughout the engagement lifecycle. Track vendor execution, delivery schedules, and performance metrics to ensure commitments are met. Drive regular technical and program sync-ups with vendors to troubleshoot issues and maintain alignment. Technical & Program Liaison (working with Project managers, Technical Leads): Act as the primary technical liaison between internal Program/I2R teams and vendors. Ensure internal requirements-performance, power, latency, interfaces, testability, security-are clearly captured and reflected in SoW and IP specs. Coordinate with Program team and maintain detailed plans for IP deliverables across programs. Ensure delivery of high-quality IP from vendors, including RTL, testbench, documentation, performance data, and errata. Coordinate with Program team on escalation and resolution of IP bugs, support requests, and change requests. Manage the lifecycle of IP versions across multiple programs (maintenance, upgrades, patches, security updates). Drive continuous improvements with vendors to meet data center-class quality and reliability expectations.

Requirements/Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 12+ years of industry experience in Product and IP management. Experience in one or more of the following technologies - PCIe, CXL, DDR (DDR4/5, LPDDR) memory subsystem IPs, RAID or storage subsystem technologies. Understanding of data center workloads, performance requirements, and system architecture trends. Background in IP governance, security requirements, and compliance frameworks. Familiarity with vendor ecosystems such as Synopsys, Cadence, Arm, Rambus, ProteanTec, etc. Strong understanding of digital IP blocks and SoC development workflows. Proven experience working with external IP vendors, SoWs, licensing models, and vendor negotiations. Excellent communication, documentation, and cross-functional coordination skills. Ability to manage multiple IPs across multiple programs in parallel.

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking, Works Alone, Works Around Others Physical Requirements:

10% walking, 10% standing, 80% sitting; 100% indoors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below: Benefits of working at Microchip The annual base salary range for this position, which could be performed in the US, is $91,000 - $247,000.•Range is dependent on numerous factors including job location, skills and experience. Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the

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To all recruitment agencies:

Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.