Job Description
Analog IC Design Engineer Alphacore Inc. - 2.5 Tempe, AZ Job Details Full-time | Internship From $90,605.52 a year 23 hours ago Benefits Relocation assistance Health insurance Dental insurance 401(k) Paid time off Employee assistance program Vision insurance 401(k) matching Flexible schedule Qualifications MATLAB Data analysis skills Verilog Electrical Engineering Debugging Full Job Description Overview Join our innovative team as an Analog/Mixed-Signal IC Design Engineer, where you will play a key role in developing high-performance
ADC/DAC, RF
transmitter/receiver, and mixed-signal signal-chain building blocks for advanced communication and sensing systems. This position focuses on deep submicron CMOS technologies such as 22 nm, 12 nm, and 7 nm, with responsibility across architecture definition, transistor-level circuit design, behavioral modeling, layout support, verification, tapeout, and silicon validation. You will work closely with system, digital, layout, packaging, and test teams to bring complex mixed-signal ICs from concept through production. This role is ideal for an experienced engineer with strong high-speed ADC/DAC design background, tapeout experience, and hands-on lab testing capability. Responsibilities Design, analyze, and optimize high-performance analog and mixed-signal IC blocks, including high-speed ADCs, DACs, RF transmitter/receiver front ends, VGAs, input buffers, reference buffers, clocking circuits, PLL-related interfaces, LVDS/SerDes interfaces, and other signal-chain building blocks. Develop transistor-level schematics and perform circuit simulations using Cadence Virtuoso/Spectre, including PVT, Monte Carlo, noise, linearity, timing, and reliability analysis. Build and maintain system-level and behavioral models using MATLAB, Verilog-A, and Verilog/SystemVerilog to support architecture exploration, calibration development, and mixed-signal verification. Work with layout engineers to guide floorplanning, device matching, shielding, parasitic-sensitive routing, and layout optimization for high-speed and high-accuracy analog/RF circuits. Perform post-layout verification and extraction using tools such as Cadence Pegasus, Calibre, and related LVS/DRC/PEX
flows. Support full-chip integration, including analog/digital interface definition, pin planning, timing requirements, power domains, reference generation, and top-level verification. Lead or support tapeout activities, including schematic/layout reviews, signoff checks, netlist verification, model delivery, and documentation preparation. Develop silicon validation plans and guide the lab testing team through ADC/DAC/RF
performance characterization, including SNDR, SFDR, ENOB, noise, linearity, bandwidth, clock jitter sensitivity, and power measurements. Analyze silicon measurement data, debug performance issues, correlate lab results with simulation/modeling results, and provide design improvement recommendations. Prepare technical documentation, datasheets, design reviews, test plans, and customer-facing technical material as needed. Experience Ph.D. in Electrical Engineering, Microelectronics, or a related field is strongly preferred. Strong experience in analog/mixed-signal IC design with proven tapeout experience in advanced CMOS technologies. Experience in 22 nm, 12 nm, or 7 nm process nodes is preferred. Demonstrated experience designing high-speed ADCs is required. Experience with DACs, RF transmitters/receivers, front-end VGAs, input buffers, reference buffers, clocking circuits, or complete mixed-signal signal chains is highly preferred. Strong understanding of ADC/DAC architectures, sampling theory, noise, distortion, clock jitter, linearity, calibration, and high-speed data-converter performance tradeoffs. Experience with MATLAB-based system modeling and calibration modeling. Experience developing and using Verilog-A behavioral models and Verilog/SystemVerilog models for mixed-signal design and verification. Proficiency with Cadence design tools, including Virtuoso schematic capture and Spectre simulation. Hands-on experience with physical verification and extraction tools such as Cadence Pegasus and Siemens Calibre. Experience with post-layout simulation, parasitic extraction review, LVS/DRC debugging, and tapeout signoff flows. Hands-on lab testing experience with high-speed ADC/DAC or RF ICs, including use of oscilloscopes, spectrum analyzers, signal generators, clock sources, power supplies, evaluation boards, and data acquisition systems. Ability to guide test engineers during silicon bring-up, debug, and characterization. Strong communication skills and ability to work across analog, digital, layout, systems, and test teams. Ability to work independently in a fast-paced development environment and drive complex IC design tasks from architecture through silicon validation. Pay:
From $90,605.52 per year Benefits:
401(k) 401(k) matching Dental insurance Employee assistance program Flexible schedule Health insurance Paid time off Relocation assistance Vision insurance Work Location:
In person
