Static Timing Analysis Engineer, Full-Chip STA

Static Timing Analysis Engineer, Full-Chip STA corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 4 years of technical experience in silicon timing closure and chip integration. Experience in one or more static timing tools (e.g., PrimeTime, Tempus). Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation. Experience delivering silicon.

Preferred qualifications:

Master's degree in Electrical Engineering, Computer Science. Experience in extraction of design parameters, QoR metrics, and analyzing data trends. Experience with ASIC design flows and methodology of static timing analysis. Delivery of high-complexity silicon in state-of-the-art technology process nodes. Knowledge of semiconductor device physics and transistor characteristics. Effective skills with scripting languages such as Tcl or Perl. About the job The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about . Responsibilities Deliver system-on-chip (SoC) Static Timing Analysis. Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs. Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area. Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.