DT Engineer

#N96

Job Title:

DFT Engineer (ATPG & Scan)

Location:

San Jose, CA (Day 1 Onsite) Job Description We are looking for an experienced DFT Engineer with strong expertise in ATPG and Scan methodologies for a Day-1 onsite role in San Jose, CA. The ideal candidate should have hands-on experience with DFT implementation, test pattern generation, silicon debug, and Synopsys tool suite. Key Responsibilities Perform DFT implementation including Scan, ATPG, simulations, and Post-Silicon diagnosis at Block and SoC level. Verify test patterns using gate-level simulations. Work closely with Synthesis, STA, and Physical Design teams to debug and resolve DFT-related issues. Partner with Test Engineers to bring up test vectors on silicon and ensure successful testing. Develop and support DFT architecture and specifications for complex chip designs. Required Skills Strong hands-on experience with: Scan

ATPG JTAG MBIST

Coverage Analysis Expertise with Synopsys tools: TetraMAX VCS Verdi DC / Fusion Compiler Experience in debugging ATPG patterns and DFT issues. Strong TCL scripting skills for automation and custom flow development. Ability to analyze silicon debug data and identify root causes effectively.

Pay:

$60.00 - $70.00 per hour

Work Location:

In person