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Lead ASIC DFT Engineer

Job

FutureTech Consultants LLC

San Jose, CA (In Person)

Full-Time

Posted 3 days ago (Updated 21 hours ago) • Actively hiring

Expires 7/3/2026

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Job Description

Title:
Lead
ASIC DFT
Engineer Location:
San Jose, CA -
Onsite Type:
Contract Job Description:
Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Required Skills & Qualifications Strong hands-on experience in
ASIC DFT
with end-to-end ownership. Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis. Experience with MBIST implementation and verification; SMS experience preferred. Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred. Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. Proven post-silicon debug and silicon bring-up experience. Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. Strong communication skills and the ability to work independently with minimal ramp-up.