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Senior Staff/Staff Power Integrity Engineer
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MediaTek Inc.
San Jose, CA (In Person)
$225,000 Salary, Full-Time
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Job Description
Senior Staff/Staff Power Integrity Engineer Apply Save Job Category Chip Design Location San Jose, CA Experience More than 6 Years Work Expe. Education Master's Degree Job Description MediaTek's Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.
Location:
San Jose, CA/Austin, TX/Portland, OR #LI-WC2 Main Requirements and Qualifications- M.S. or Ph.D. in Electrical Engineering or a related field.
- 6+ years of experience in power delivery and power integrity analysis for high performance SoCs and advance packaging technologies.
- Proficiency in using simulation and analysis tools for power integrity, including PowerSI, PowerDC, H-Spice and ADS
- Experience with PCB design and layout for power integrity, including layer stack-up assignment, power plane partitioning, component selection and placement, as well as micro-via and plated through-hole (PTH) design.
- Proficiency in scripting languages such as Skill, TCL, Python, and Matlab for design automation Salary range: $180,000- $270,000.