Senior DFT Engineer

Senior DFT Engineer at

PHIZENIX

Senior DFT Engineer at

PHIZENIX

in Santa Clara, California Posted in about 22 hours ago.

Type:

full-time

Job Description:

Job Description What You Can Expect We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs. Key Responsibilities Lead hands-on scan DFT implementation, including scan insertion, stitching, SSN implementation, and IJTAG (IEEE 1687) integration Perform scan DFT verification, debug, and DFT DRC closure across complex SoC designs Debug and resolve scan-related DRCs, connectivity issues, and control signal problems Run, analyze, and debug SpyGlass DFT/RTL checks in collaboration with design teams Generate, simulate, and debug ATPG scan patterns; analyze results and drive coverage closure Develop and validate DFT timing constraints (scan, shift, capture, and test modes) Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis Optimize scan implementations for improved pattern efficiency and test quality Support hierarchical scan integration at block and SoC levels Collaborate closely with RTL and Physical Design teams to resolve scan-related challenges Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug Assist with ATE pattern conversion and scan debug activities Required Qualifications Bachelor's degree in Computer Science, Electrical Engineering, or related field with 5-10 years of experience, OR Master's/PhD with 3-5 years of experience 8+ years of hands-on experience in DFT scan implementation Strong expertise with Siemens Tessent, including scan insertion, verification, ATPG, and coverage analysis Hands-on experience with IJTAG (IEEE 1687) and Scan Streaming Network (SSN) Strong understanding of IEEE 1149.x, IEEE 1500, and

IEEE 1687

standards Proven experience in resolving scan DFT DRCs and driving coverage closure Strong TCL scripting skills for automation and flow development Experience in developing and validating scan/test timing constraints End-to-end DFT lifecycle experience from RTL/netlist to silicon debug Strong debugging, ownership, and problem-solving skills Excellent verbal and written communication skills Preferred Qualifications Experience with scan compression and advanced scan architectures Post-silicon experience including pattern bring-up, debug, silicon characterization, and yield learning Experience mentoring junior engineers or owning DFT scan signoff