Analog IC Layout Engineer

Analog IC Layout Engineer Neuralink - 2.3 South San Francisco, CA Job Details Full-time $83,000 - $139,000 a year 1 day ago Benefits Commuter assistance Paid holidays Health insurance Dental insurance 401(k) RSU Parental leave Vision insurance Qualifications Automation Mid-level C Energy efficiency & conservation Design for manufacturability (DFM) Cross-functional collaboration 2 years

Python Shell Scripting Full Job Description About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include: Crafting state-of-the-art layouts for mixed-signal and analog circuits Amplifiers Filters Switched capacitor circuits Oscillators Data converters Power management circuits Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

2+ years of experience in analog and mixed-signal IC layout design 1+ year experience with FinFET technologies Ability to identify the best approach to solving problems

Preferred Qualifications:

Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption Understanding on failure-prone circuit and layout structures Experience with analog DFM standards Experience with layout P-cell design and implementation Experience with layout automation

What We Offer:

Full-time employees are eligible for the following benefits listed below. An opportunity to change the world and work with some of the smartest and most talented experts from different fields Growth potential; we rapidly advance team members who have an outsized impact Excellent medical, dental, and vision insurance through a PPO plan Paid holidays Commuter benefits Meals provided Equity (RSUs)

• Temporary Employees & Interns excluded 401(k) plan
• Interns initially excluded until they work 1,000 hours Parental leave
• Temporary Employees & Interns excluded Flexible time off
• Temporary Employees & Interns excluded