Hardware FPGA Design Engineer - Acacia (Hybrid)
Job
Cisco
Remote
$180,850 Salary, Full-Time
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Job Description
The application window is expected to close on: 02/12/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on: 3/31/26. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three days per week at Cisco's Maynard, MA office. Meet the Team Acacia, now part of Cisco, designs intelligent optical transceivers using sophisticated signal processing and photonic integration for >1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunicat ion networks. The team is a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-function ally with our Hardware, Software, Optics, and manufacturing teams. Your Impact You are a high-energy FGPA Design engineer who loves to work on complex communications products. You are a team player with a startup mentality who loves to challenge the status quo with creation and innovation. You can figure things out by yourself, but you are comfortable to participate in our friendly and team-oriented collaboration approach to learn from others. You are not shy to point out how we can be more effective as a team, and yet you are open to similar suggestions by your team members to foster mutual growth for all.
- Design/Verify FGPAs For Acacia's Product and Evaluation platform
- Write Python routines for Test Development and Automation
- Contribute to FPGA Emulation of ASIC Blocks
- Contribute to our custom
ASIC RTL
code Minimum Q ualifications:- Bachelors +8 years of experience, or Masters +6 years of experience, or PHD +3 years of experience of related experience or higher with minimum
- 5+ years of FPGA design and verification experience
- Experience in Verilog RTL coding and synthesis for FPGAs
- Experience with Python and Linux
- Experience designing interfaces with Processors, SPI & I2C devices, MDIO, high speed SERDES, etc.
- Experience in Xilinx® design tool chain for design, place, and route (ISE®, Vivado® suite) Preferred Q ualifications:
- C/C++ and experience coding with embedded MCUs
- Experience in designs and timing closure with multiple clock domains
- Experience work in labs and experience with test equipment to help with board level and FPGA bring up
- Experience with analog components (OpAmps, DACs/ADCs, etc.)
- Experience implementing digital control loops and DSP functions
- Experience with Xilinx FPGA families such as Ultrascale+
- Experience with Synopsys VCS simulation and Synplify® synthesis tools for FPGAs
- Expertise in creating FPGA implementation s from
ASIC RTL
code- Expertise in digital design of standard cell ASICs
- Experience presenting technical information to technical and non-technical audiences.
Canada:
The starting salary range posted for this position is $148,800.00 to $212,900.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation- , equity, or benefits.
- receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.
New York City Metro Area:
$168,800.00 - $277,400.00 Non-Metro New York state & Washington state: $148,800.00 - $248,200.00- For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
- Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
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