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ASIC/RTL Design Engineer 2

Job

Cynet Systems

San Jose, CA (In Person)

$126,880 Salary, Full-Time

Posted 3 days ago (Updated 18 hours ago) • Actively hiring

Expires 7/4/2026

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Job Description

We are looking for
ASIC/RTL
Design Engineer 2 for our client in San Jose, CA .
Job Title:
ASIC/RTL
Design Engineer 2
Job Location:
San Jose, CA Job Type:
Contract Job Overview:
Pay Range:
$60/hr - $62/hr The position involves working on advanced digital CMOS processes and leading the design of state-of-the-art SoCs.
Requirement/Must Have:
Experience in SoC Architecture. Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces.
Responsibilities:
Lead and participate in the design of leading edge SoCs. Contribute in all aspects of SoC design including chip definition, architecture development, and modeling. Develop micro-architectural specifications. Convert micro-architectural specifications to logic implementation. Engage in verification, emulation, debug, synthesis, and timing closure. Interface with physical execution, software, and silicon bring-up teams. Nice to
Have:
Strong communication and documentation skills. Good organizational, time management, and multitasking skills. Strong initiative and discipline to follow-through. Technical leadership experience.