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Principal Memory Design Engineer/Senior Technical Manager
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MediaTek Inc.
San Jose, CA (In Person)
$261,000 Salary, Full-Time
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Job Description
Principal Memory Design Engineer/Senior Technical Manager Apply Save Job Category Chip Design Location San Jose, CA Experience More than 8 Years Work Expe. Job Description MediaTek's advanced memory design team in San Jose, CA is seeking a highly experienced memory design engineer to architect and define memory circuits. This role focuses on high-performance compute (HPC) ASIC solutions for Data Center AI and Networking, as well as designing energy efficient edge AI Accelerators.
- Work in close partnership with leading Data Center AI ASIC customers in North America to co-develop embedded memory architectures and circuits on advanced technology nodes.
- Collaborate with product engineering, technology development and architecture teams to define, design, and deliver high-performance, customized semiconductor memory solutions — including SRAM, TCAM, Compute-In-Memory (CIM), and Near Memory Compute (NMC) macros — tailored to diverse PPA requirements for Data Center AI, Networking, and Edge AI applications.
- Lead Design Technology Co-Optimization (DTCO) and pathfinding initiatives for semi-custom and custom SRAM designs.
- Lead the end-to-end design of dual-rail custom memories, ensuring all customer performance, power, and area (PPA) specifications are fully satisfied.
- Drive innovation by designing and integrating specialized circuits and features to achieve industry-leading PPA in both custom and compiler-generated memories.
- Provide mentorship and technical direction to other designers, while remaining hands-on in digital circuit design with a focus on memory architectures.
- Evaluate and implement new design methodologies and tools to enhance productivity and quality.
- Demonstrate strong organizational skills and the ability to work independently, effectively managing multiple tasks, and collaborating with global design and CAD teams. Main Requirements and Qualifications
- PhD or master's degree in electrical engineering or related field.
- 10+ years of hands-on experience designing embedded memories (SRAM, TCAM) for high-performance processors or ASICs in advanced technology nodes (A14/A16/2nm/3nm/5nm).
- Proven track record of delivering innovative solutions, including published papers and patents, with a strong understanding of the technology roadmap and market trends for embedded memories.
- Experience with DTCO and pathfinding for semi-custom and custom designs is desirable.
- Deep expertise in digital circuit design techniques, particularly in FinFET and Gate-All-Around technologies.
- Experience with the full design cycle of SRAM and memory compiler development.
- Skilled in developing comprehensive design verification and test plans.
- Familiarity with Logic Equivalence Checking (LEC) tools such as ESPCV.
- Capable of reviewing and coordinating layout activities & IR-EM signoff.
- Familiarity with transistor level STA tools such as NanoTime.
- Demonstrated experience in silicon debugging and bring-up.
- Experience with semi-custom design flows, including RTL synthesis, DV, APR, and STA, is desirable.
- Proficient in scripting languages such as Perl and Python.
- Strong analytical & problem-solving skills with excellent communication & leadership abilities.
- Eager to work collaboratively with cross-functional teams across global locations.