Senior ASIC Design Engineer

Job Requirements Saratoga, CA Secret Polygraph Unspecified Career Level not specified $250,000 - $290,000 Job Description Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high-performance networking ASICs. The ideal Senior ASIC Design Engineer will bridge the gap between high-level system design and ASIC implementation to help shape the future of data communication. Responsibilities for the

Senior ASIC Design Engineer:

Work with the CTO and engineering teams to translate system-level requirements into detailed ASIC architecture. Lead architectural modeling and analysis to ensure optimal throughput, latency, and power efficiency. Collaborate with RTL, Verification, Physical Design, and Firmware teams to ensure seamless implementation. Drive integration of high-speed I/O and third-party IPs into the ASIC design. Qualifications for

Senior ASIC Design Engineer:

10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc) Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance. Deep understanding of networking protocols (Ethernet, TCP/IP, VLAN, MPLS, RoCE) and their hardware implications. Proven experience in architecture design, performance modeling, and architectural trade-offs. Familiarity with high-speed I/O (PCIe Gen5/Gen6, SerDes) and software control plane interfaces. Experience across the full ASIC development lifecycle-from concept to silicon validation. Master's degree in Electrical Engineering or related field required. Compensation/Benefits for the

Senior ASIC Design Engineer:

Salary Range:

$250,000 - $290,000 annually (based on experience and qualifications)

Comprehensive Benefits:

Medical, Dental, Vision, 401K, PTO, Sick Leave (if required by law), and Holidays This job opens for applications on 4/27/2026. Applications for this job will be accepted for at least 30 days from the posting date.

Keywords:

ASIC, ASIC

Architect, Networking

ASIC, AI

Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC #LI-BR1 #

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group id: 10430981 Apply now