Job Description
Senior ASIC Design Engineer, Google Cloud corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with three or more SoC projects/cycles. Familiarity with the full ASIC flow (DFT, synthesis, PnR), SerDes behavior, and scripting (Python, Tcl, or Perl) to drive technical execution. Expert knowledge of NoC/Memory architecture, flow control, and performance tuning. Proven ability to lead cross-functional efforts with software and system hardware teams, from initial library RTL development through to silicon bring-up. Advanced RTL design skills with mastery of multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning. About the job The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about . Responsibilities Drive the complete RTL life-cycle from initial microarchitecture, coding, and documentation to sign-off readiness (Lint, CDC, synthesis) for high-performance designs meeting strict PPA targets and quality guidelines. Collaborate with system architects to align on chip-level bandwidth, latency, and power objectives, and partner with the Verification and Physical Design teams to define test plans and achieve timing closure. Identify test requirements, define methodology/tools, and execute testing of silicon systems; drive protocol resolution and lead post-silicon bring-up to validate link integrity and subsystem performance. Influence designs to enhance testing, validation, and debugging capabilities, while establishing third-party IP requirements and driving the selection process. Develop and maintain policies, processes, procedures, methods, and documentation for silicon deliverables to enhance efficiency, productivity, and project sustainability.
