CAD Engineer - PDV

Job Listing ID:

4475421

Job Title:

CAD Engineer -

PDV Application Deadline:

Open Until Filled

Job Location:

Beaverton

Date Posted:

04/18/2026

Hours Worked Per Week:

Not Provided Shift:

Not Provided Duration of Job:

Either Full or Part Time, more than 6 months You may contact this employer directly. (Obtain the contact information to print or add to your jobs.)

Job Summary:

Role Number:

200658358-0505 Summary Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones. You will also have opportunities to develop ML/LLM based automations and solutions. Description -Develop, improve and maintain various aspects of physical verification flow and methodology-Coordinate the effort of validating flows, improving for custom checks and data generation-Work with the design and PD teams to facilitate the chip design process-Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs-Collaborate with tool vendors and foundries for PDK performance enhancements Minimum Qualifications Minimum requirement of BS +10 years of relevant industry experience. Preferred Qualifications Previous industry experience in Silicon chip design flows Tapeout support and IP/SOC level PDV debug experience in various technology nodes Expert in Calibre/ICV runset coding for

DRC/LVS/ERC/MFILL

Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or C Experience with flow automation and development in advanced nodes. Rule coding in PERC is a plus. Knowledge of ML/LLM is a plus. Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Job Classification:

Computer Hardware Engineers Access our statewide or regional occupation report for more information about wages, employment outlooks, skills, training programs, related occupations, and more. Compensation

Salary:

Not Provided Job Requirements

Experience Required:

 See Job Summary

Education Required:

None

Minimum Age:

N/A Gender:

N/A