Timing Design Engineer

Job Listing ID:

4477433

Job Title:

Timing Design Engineer Application Deadline:

Open Until Filled

Job Location:

Beaverton

Date Posted:

04/22/2026

Hours Worked Per Week:

Not Provided Shift:

Not Provided Duration of Job:

Either Full or Part Time, more than 6 months You may contact this employer directly. (Obtain the contact information to print or add to your jobs.)

Job Summary:

Role Number:

200657989-0505 Summary Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something. Description As an

ASIC STA

Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self-starter and highly motivated to be successful at Apple. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Job Classification:

Electronics Engineers, Except Computer Access our statewide or regional occupation report for more information about wages, employment outlooks, skills, training programs, related occupations, and more. Compensation

Salary:

Not Provided Job Requirements

Experience Required:

 See Job Summary

Education Required:

None

Minimum Age:

N/A Gender:

N/A