Packaging Design Engineer
Job
Actalent
Remote
$156,000 Salary, Full-Time
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Job Description
Job Title:
Packaging Design Engineer (ASIC Packaging - Cadence APD) Job Description This role focuses on the design and validation of high‑performance semiconductor packages using Cadence Advanced Package Designer (APD). The Packaging Design Engineer develops advanced package substrates for flip‑chip BGAs and 2.5D/3D structures, ensuring robust package‑level reliability, thermal performance, and signal integrity. The engineer produces detailed layout designs, performs comprehensive verification checks, and prepares manufacturing‑ready data while collaborating closely with foundries, OSATs, and ASIC design teams. Responsibilities Design and develop advanced semiconductor packages, including flip‑chip BGA and 2.5D/3D structures, using Cadence APD. Create, refine, and maintain package substrate layouts for BGA and flip‑chip ICs, ensuring compliance with electrical, mechanical, and manufacturing requirements. Apply SI/PI principles and constraint management to support high‑speed I/O packaging, signal integrity, and power integrity performance. Perform package‑level thermal management analysis and incorporate thermal considerations into layout and stack‑up decisions. Execute Design Rule Checks (DRC), Layout vs. Schematic (LVS), and connectivity checks to validate design correctness and manufacturability. Use Cadence Allegro APD/SIP or comparable packaging design tools to generate accurate and complete design databases and manufacturing files. Collaborate with foundries, OSATs, and ASIC design teams to define package requirements, resolve design issues, and support design‑for‑manufacturability. Ensure that high layer count, large‑body flip‑chip BGA packages meet performance, reliability, and cost targets. Support design validation activities, including reviews of SI/PI, thermal, and reliability constraints at the package level. Prepare and deliver documentation and data packages required for fabrication, assembly, and test of advanced semiconductor packages. Essential Skills Bachelor's degree in Electrical Engineering (preferred) or Mechanical Engineering from a four‑year college or university. 3-5 years of current, hands‑on experience with Cadence Advanced Package Designer (APD) focused on advanced package substrates such as BGAs and flip‑chip ICs. Proven ability to perform package layout and design for advanced semiconductor packages. Strong experience in substrate design, including stack‑up definition and routing for complex packages. Solid understanding and practical application of signal integrity (SI) and power integrity (PI) principles and constraint management in package design. Experience with thermal management considerations in high‑performance packaging. Proficiency in high‑speed I/O packaging techniques and constraints. Strong understanding of high layer count, large‑body flip‑chip BGA packaging technology. Ability to perform Design Rule Checks (DRC), Layout vs. Schematic (LVS), and connectivity checks accurately and efficiently. Proficiency in Cadence Allegro APD/SIP or comparable electronic packaging design tools. Experience collaborating with foundries, OSATs (Outsourced Semiconductor Assembly and Test), and ASIC design teams on package development. Additional Skills & Qualifications 3-5 years of experience with SI/PI simulations using Ansys HFSS. Experience using Ansys tools for advanced electromagnetic and signal integrity analysis. Working knowledge of bootloaders and bringing up new hardware platforms, including using or implementing bootloader solutions. Experience or exposure to the medical device industry is a plus. Strong analytical and problem‑solving skills with attention to detail in complex package designs. Ability to communicate technical concepts clearly and collaborate effectively in a cross‑functional engineering environment. Work Environment This is a remote role, allowing you to contribute from your preferred location while collaborating with global engineering teams. You will work in a highly technical, design‑driven environment focused on advanced semiconductor, enterprise software, and security solutions that power complex IT infrastructures worldwide. Daily work centers on modern EDA tools such as Cadence Advanced Package Designer (APD), Cadence Allegro APD/SIP, and Ansys HFSS, with frequent virtual collaboration with foundries, OSAT partners, and ASIC design teams. Job Type & Location This is a Contract position based out of Broomfield, CO. Pay and Benefits The pay range for this position is $65.00 - $85.00/hr. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:- Medical, dental & vision
- Critical Illness, Accident, and Hospital
- 401(k) Retirement Plan - Pre-tax and Roth post-tax contributions available
- Life Insurance (Voluntary Life & AD&D for the employee and dependents)
- Short and long-term disability
- Health Spending Account (HSA)
- Transportation benefits
- Employee Assistance Program
- Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a fully remote position.
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