Principal SoC Design Engineer, HBM

Req ID:

JR102410

Principal SoC Design Engineer, HBM Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet aggressive power, performance, area, and schedule targets. This is a hands‑on technical role focused on RTL design, IP integration, debug, and pre‑/post‑silicon support. Key Responsibilities

• ### Key Responsibilities
• Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic).
• Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations.
• Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues.
• Work closely with physical design teams to address synthesis, timing, power, and floorplanning considerations.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues.
• Contribute to design documentation, block specifications, design reviews, and collaborate cross‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable designs; continuously improve design quality, reusability, and development efficiency through best practices and automation. ### Minimum Qualifications
• Strong experience in digital SoC design and RTL development.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and design sign‑off considerations.
• Working knowledge of design verification concepts and debug workflows.
• Experience integrating complex IP blocks into large SoCs; familiarity with EDA tools from Cadence, Synopsys, and/or Siemens; programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting); ability to work effectively in a global, cross‑functional engineering environment; strong analytical and problem‑solving skills with attention to detail. ### Preferred Qualifications
• Experience with HBM, DRAM, or memory‑centric SoC designs.
• Familiarity with high‑speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field; minimum 10 years of experience in a related field; proven ability to mentor and develop junior engineers.

Job Profile(s): Systems Design Engineer 5

Relocation Level:

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