Skip to main content
Tallo logoTallo logo
Apply for this opportunity

This job application is on an outside website. Be sure to review the job posting there to verify it's the same.

Apply Offsite

Job Title: Senior Physical Design / STA Engineer - W2

Job

MASH Pro Tech

Carmel-by-the-Sea, CA (In Person)

Full-Time

Posted 1 week ago (Updated 6 days ago) • Actively hiring

Expires 6/29/2026

Review key factors to help you decide if the role fits your goals.
How is this calculated?
Pay Growth
?
out of 5
Not enough data
Not enough info to score pay or growth
Job Security
?
out of 5
Not enough data
Calculating job security score...
Total Score
82
out of 100
Average of individual scores

Were these scores useful?

Skill Insights

Compare your current skills to what this opportunity needs—we'll show you what you already have and what could strengthen your application.

Job Description

Job Title:
Senior Physical Design /
STA Engineer Location:
Bay Area, CA / Austin, TX - CA 1st preference
Employment Type:
Long-Term Contract (W2 Only) Position Summary We are seeking a Senior Physical Design / STA Engineer with strong hands-on experience in physical design and static timing analysis for advanced semiconductor projects. The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs. Responsibilities Perform full-chip and block-level physical design implementation. Execute Static Timing Analysis (STA) and timing closure activities. Work on floorplanning, placement, clock tree synthesis (CTS), routing, and signoff. Analyze and resolve setup/hold timing violations. Collaborate with RTL, DFT, and backend design teams. Support low-power and high-performance design optimization. Participate in design reviews and debugging activities. Ensure designs meet power, performance, and area (PPA) targets. Required Skills 7+ years of experience in Physical Design and STA. Strong expertise in timing closure and signoff flows. Experience with industry-standard EDA tools for STA and physical design. Knowledge of synthesis, floorplanning, CTS, routing, and ECO flows. Strong understanding of ASIC/SoC design methodologies. Experience with advanced technology nodes is preferred.