WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
Job Description:
Job Description Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure across multiple corners and modes. Analyze and resolve setup, hold, transition, capacitance, and noise violations. Develop and maintain timing constraints (SDC) and STA signoff methodologies. Perform EMIR (Electromigration & IR Drop) analysis and closure. Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout. Debug physical design issues and drive design convergence within project schedules. Required Skills Strong experience in Physical Design and PnR flow.
Hands-on expertise in:
o Floorplanning o Placement & Optimization o Clock Tree Synthesis (CTS) o Routing o Timing Closure o Static Timing Analysis (STA) o Timing Constraints (SDC) o EMIR Analysis o PPA Optimization Experience with industry-standard EDA tools such as: o Synopsys Fusion Compiler / ICC2 o PrimeTime o Cadence Innovus (optional) o RedHawk / Voltus (EMIR) Good understanding of low-power design techniques and signoff methodologies. Preferred Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering. Experience in advanced nodes (7nm/5nm/3nm preferred). Strong debugging and problem-solving skills. Experience working with cross-functional silicon teams.
Mandatory Skills:
VLSI Physical Place and Route .
Experience:
3-5 Years . The expected compensation for this role ranges from $45,000 to $121,000 . Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options. Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law. Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. #body.unify div.unify-button-container .
