Principal Design Engineer

Part of the design team driving multiple facets of high-performance, high-bandwidth designs Work on IP microarchitecture specification Perform RTL (Register Transfer Level) design and synthesis Support SoC (System on Chip) integration across different subsystems Collaborate with architecture, verification, and physical design teams Ensure designs are implemented and verified according to specifications Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure. 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. 5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug 5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic Die to die IP design CPU or graphics core design. Complex algorithmic designs for AI usages Script development.