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CPU Physical Design Engineer

Job

Apple

Beaverton, OR (In Person)

$249,750 Salary, Full-Time

Posted 03/11/2026 (Updated 2 weeks ago) • Actively hiring

Expires 5/27/2026

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Job Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design.

DescriptionAs a CPU Physical Design Engineer, you will drive or participate in the following:
  • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals
  • Will be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield
  • Will work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design
  • Will work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability
  • Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPAPreferred QualificationsExperience in low power, high frequency physical design techniques leveraging advanced syn/PnR tool features, and best in class physical design methodologyExperience using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with timing budgeting, floor-planning, physical integration, and verification to converge complex designsKnowledge in deep sub-micron technology, along with its implications to timing, power, and areaExcellent communication and interpersonal skillsAbility to work independently and/or lead a physical design partition in collaboration with x-functional teamsMinimum QualificationsMinimum BS and 10+ years of relevant industry experienceExperience in logic design and digital circuitsExperience with Perl or TCLApple is an equal opportunity employer that is committed to inclusion and diversity.
We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .Pay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note:
Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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