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Custom HBM Physical Design Engineer, Member of Technical Staff (MTS)
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Micron Technology
Richardson, TX (In Person)
$270,500 Salary, Full-Time
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Job Description
Req ID:
JR103996
Custom HBM Physical Design Engineer, Member of Technical Staff (MTS) Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Custom HBM Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities- Own physical implementation for SoC blocks and/or top-level, including floor planning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff, including
DRC/LVS, IR
drop/EM, and timing signoff, addressing violations efficiently.- Work with packaging, assembly, test, probe, and manufacturing stakeholders to ensure design meets manufacturability and quality requirements.
- Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development. Required Qualifications
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
- Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Strong scripting/automation skills using Python, TCL, Perl, and/or shell. Preferred Qualifications
- Experience with
HBM / DRAM
adjacent SoC designs, or memory-subsystem-heavy SoCs.- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 15 years of experience in a related field.
Machine Learning Engineering MTS Relocation Level:
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