Analog and RF layout engineer

Seeking an experienced Analog/RF Layout Engineer with 6+ years of expertise in designing and leading complex IC layouts for high-speed applications using advanced CMOS FinFET technologies (7nm and below). The role involves block-level and chip-level layout development, ensuring high performance, reliability, and compliance with design rules.

Key Responsibilities:

Develop and lead complex IC layouts for high-speed analog/mixed-signal designs. Perform floorplanning, block-level routing, and top-level chip assembly. Design layouts for transceivers, PLLs, CMOS drivers, and high-speed data converters. Apply advanced layout techniques including thermal-aware design and electromigration considerations. Collaborate with cross-functional teams to ensure design integrity and performance.

Mandatory Skills:

Expertise in advanced CMOS FinFET technologies (7nm and below) at block and chip level. Strong experience in floorplanning, routing, and full-chip assembly. Proficiency in EDA tools from Cadence, Mentor, and Synopsys. Solid understanding of analog/RF and mixed-signal layout best practices.