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Principal DV Engineer
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MediaTek Inc.
San Jose, CA (In Person)
$240,050 Salary, Full-Time
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Job Description
Principal DV Engineer Apply Save Job Category Chip Design Location San Jose, CA Experience More than 6 Years Work Expe. Education Master's Degree Job Description
- Lead the DV effort of a high-end CPU project.
- Architect and implement testbenches and their components using UVM-based methods.
- Lead the effort in building in-house BFMs, unit-level testbenches and stimulus.
- Work with the design team to create testplans. Implement checkers/assertions/coverages. Drive directed testcases and controlled random testcases based on the testplans.
- Work on the core-level verification using in-house testbenches. Triage bug reports, profile failure cases, check functional coverage and drive the effort of directed testcase generation. Main Requirements and Qualifications
- Masters/Bachelor or above degree in electronic/electrical engineering, computer science, mathematics or physics.
- 10+ years of verification experiences
- Familiar with industry instruction set architects such as ARM, RISC-V and etc.
- Hands-on experience in the field of cache coherent fabric verification
- Solid experiences with SystemVerilog, UVM and etc.
- Experiences with major processor blocks.
- Scripting capability is highly desired.
- Good written and verbal communication skills
- Good cross site and cross function execution skills Salary range: $179,100-$301,000 Employee may be eligible for performance bonus, short and long term incentive programs.