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Design Verification Engineer

Job

Reveille Technologies

Santa Clara, CA (In Person)

Full-Time

Posted 1 week ago (Updated 1 week ago) • Actively hiring

Expires 6/28/2026

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Job Description

No Contract Only Fulltime Title:
Design Verification Engineer Loc:
Santa Clara CA(Weekly 5 days onsite)
Type:
Fulltime Key Responsibilities:
DV Engineer with strong expertise in SystemVerilog, UVM, and AMBA protocols. Experienced in building IP/SoC testbenches, writing test plans from design specs, and closing functional/code coverage. Skilled in power-aware (UPF/CPF) simulations, debugging RTL failures, and collaborating across DFT, PD, and post-silicon teams to ensure high-quality design delivery.
Note:
Only local candidate's are eligible to apply for this role. Praveenkumar