Hiring DFT Engineer in Santa Clara CA | Hybrid | FTE/Contract

Hi, Please check the below job

DFT Engineer Location:

Santa Clara, CA (Hybrid 3 Days Onsite)

Employment Type:

Full-Time / W2

Contract Experience:

3 12

Years Industry:

Semiconductor / VLSI / ASIC Design Job Overview We are seeking a highly motivated DFT (Design for Test) Engineer to join a fast-growing semiconductor team developing next-generation SoCs and ASICs. The ideal candidate will be responsible for architecting, implementing, and validating DFT solutions for complex designs at advanced technology nodes. This is an excellent opportunity to work on cutting-edge silicon products in a collaborative environment alongside industry-leading design, verification, and physical implementation teams. Key Responsibilities Develop and implement DFT architectures for complex SoC and ASIC designs. Perform scan insertion, scan compression, and ATPG generation. Analyze and improve fault coverage for manufacturing tests. Support JTAG, Boundary Scan, MBIST, and LBIST implementation. Collaborate with RTL, Verification, Physical Design, and Test Engineering teams. Execute DFT verification using simulation and formal methodologies. Drive DFT signoff activities and ensure testability requirements are met. Debug scan chain, ATPG, and silicon bring-up issues. Support post-silicon validation and production test activities. Work closely with EDA vendors and internal teams to optimize DFT flows. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3 12 years of experience in DFT engineering for ASIC/SoC development. Strong understanding of Scan Architecture, ATPG, and Fault Models. Hands-on experience with Scan Insertion and Scan Compression techniques. Experience with JTAG, Boundary Scan, MBIST, and LBIST methodologies. Knowledge of RTL design using Verilog/SystemVerilog. Familiarity with ASIC design flow from RTL to GDSII. Strong debugging and problem-solving skills. Preferred Skills Experience with advanced technology nodes (16nm, 7nm, 5nm, 3nm). Exposure to low-power DFT methodologies. Knowledge of IEEE 1500 and

IEEE 1687

standards. Understanding of timing closure and physical design impacts on DFT. Experience working with high-performance CPU, GPU, AI/ML, Networking, or Automotive SoCs. EDA Tools Experience Synopsys DFT Compiler Synopsys TestMAX / TetraMAX Cadence Modus Tessent Scan / Tessent MBIST PrimeTime VCS / Xcelium Verdi / SimVision