Principal Physical Design Verification/ESD Engineer

Principal Physical Design Verification/ESD Engineer Ampere Computing - 3.5 Portland, OR Job Details Full-time $182,000 - $273,000 a year 16 hours ago Benefits Paid holidays Dental insurance Flextime Vision insurance Qualifications Bachelor's degree in electrical engineering Engineering Electrical engineering Master's degree 8 years Bachelor's degree ANSYS Doctor of Philosophy Computer Engineering Master's degree in electrical engineering Design for manufacturability (DFM) Senior level Electrical Engineering Semiconductor experience Debugging Full Job Description Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd love to have you apply!

About the role:

As a member of the PDV Team, you'll own chip-level physical design verification, physical verification flow automation, physical design reviews and ESD coverage. What you'll achieve: Partition and chip-level level ownership of physical design verification (PDV), and physical design reviews Execute and debug final verification flows in preparation for gds tape out delivery on FinFet designs (DRC, LVS,DFM, Antenna, Density Fill Routines, XOR, etc.) ESD Verification and Sign-off at partition and chip level Design enhancements and DFM techniques Package level physical verification

LVS / DRC

check coding Support all PDV sign-off scripts at partition and at chip-level Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam About you: Background with FinFets and multi exposure metallization is required Familiarity with Cadence and Siemens tools is required Shell, Skill, Calibre and other programming knowledge Familiarity with Physical Verification flow automation Familiarity with ESD coverage techniques and verifications flows (Calibre PERC, Ansys Pathfinder) Familiarity with DFM techniques for yield enhancements Familiar in identifying and addressing issues often found at the chip level, some of which include: Density Latch up triggered failures Abutment conflicts Data integrity Short isolation and open/swapped nets Electrical or Computer Engineering - Bachelor's degree & 8 years of related experience; or Master's degree & 6 years; or PhD & 3 years What we'll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $182,000 and $273,000, except in the San Francisco Bay Area where the range is between $195,000 and $292,000. Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit highlights include:

Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future. Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance. A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process. #LI-TC #LI-Hybrid Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.