FPGA Verification Engineer

Job Requirements Arlington, VA Jessup, MD Top Secret/SCI Full Scope Polygraph Mid Level Career (5+ yrs experience) Salary not specified Join Premium to unlock estimated salaries

Job Description Location:

Arlington, VA (HQ2) or

Jessup, MD Clearance:

Active TS/SCI with polygraph required

Citizenship:

US Citizen required Scope of Work Develop and execute verification strategies for FPGA-based systems supporting AWS infrastructure. The contractor will build UVM-based verification environments, develop testbenches, and drive coverage closure for 100G+ networking solutions on advanced FPGA platforms. Key Responsibilities

• Develop UVM/SystemVerilog verification environments and testbenches for FPGA designs
• Create and execute verification plans with functional coverage models and assertions
• Drive coverage closure to completion (functional, code, and assertion coverage)
• Debug RTL failures in simulation and on hardware targets
• Develop constrained-random and directed test sequences for protocol verification (e.g., AXI, Ethernet)
• Perform regression analysis and coverage gap identification
• Collaborate with design engineers on architecture reviews and interface specifications
• Support hardware bring-up and debug on FPGA targets Required Qualifications
• BS in Electrical Engineering or related field
• 5+ years

FPGA/ASIC

verification experience

• SystemVerilog required
• 5+ years with UVM-based verification (constrained-random, coverage-driven methodologies)
• Demonstrated experience driving coverage closure to completion
• Strong UVM testbench architecture skills (agents, sequences, scoreboards, coverage models)
• Proficiency in SystemVerilog assertions (SVA) and simulation tools (Synopsys VCS, Mentor Questa, or equivalent)
• Experience verifying high-speed networking or datapath designs
• Knowledge of standard bus protocols (AXI, AXI-Stream, Ethernet)
• Active TS/SCI with polygraph (US Citizen) group id: 91164107 N Name Hidden Recruiter Apply now