FPGA Design/Verification Engineer

Description:

The selected candidate will be responsible for

ASIC & FPGA

verification utilizing UVM. Key activities you will accomplish in this role: Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test. Support technical reviews and be able to present to internal and external customers Devise a unique verification plan for a given design. Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment. Document verification plan and results. Work with an independent verification team to resolve bugs found in the design. To be effective in this role, you will need:

ASIC/FPGA

verification experience with modern verification methodologies such as UVM, OVM or VMM. 3 years professional experience. Active DoD Secret clearance Work Schedule 5/40-1st Shift Security Clearance Comments Active DoD Secret - NGI-HQ085621-C-0001 Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services. Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.