Synopsys power flows (Only W2)

Total Headcount 1 Job Description Core Skills 1. Understanding of Synopsys power flows (PTPX + PRRTL) 2. Some PD background or understanding of netlist, UPF, SPEF 3. Scripting knowledge

• Python (required) + tcl.

Excel/Gsheet (nice to have) 4. Power optimization experience or understanding design+uArch for NoC+Clocking 5. Some background on CTS Second set of skills 1.Understanding of power fundamentals and experience with Synopsys power estimation tools (PrimePower, PPRTL). 2.Familiarity with Syn-PnR flows using Synopsys Fusion Compiler (and RTL-A). 3.Ability to develop and maintain automation scripts (preferably in Python) to streamline design flows and improve process efficiency. 1. 3-6 years of experience in Primepower or PowerArtist or Voltus

• Mandatory 2. Working knowledge of Tcl
• Mandatory 3. Python knowledge
• Good to have Annual Salary Expected $205K / Annum Band B2/C1 Responsibilities/Qualifications Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design at different design stages from RTL to gate-level netlist.

Contribute to develop, improve, and automate power analysis flows Investigate power inefficiencies and provide feedback to design teams Present the results in a weekly meeting to wider audience Work closely with physical design team for clock tree, floorplan and physical implementation optimization Participate in memory power optimization through memory selection and traffic optimization Perform Synthesis and Physical design trials for optimal PPA recipes

Minimum Qualifications:

RTL2GDSII

design flow usage & development in advanced technology nodes (7nm and below) Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF usage. Experience in power analysis and reduction using PrimeTime PX/PrimePower Proficiency in scripting languages such as Python and/or Perl is required Proficiency with TCL is required Familiarity with low power implementation techniques, clock gating, power gating etc. Good written and verbal communication skills Familiarity with memories (SRAM/DRAM/RF/Flop based fifos)

Preferred Qualifications :

Experience with synth, PnR flows Power and performance implications with latest technology nodes Proficiency with version control systems Experience with rtl power optimization using tools such as Power-Artist Experience with library characterization tools and analysis Experience with FSDB analysis for design profilin