RTL Design Engineer, Machine Learning Accelerators

RTL Design Engineer, Machine Learning Accelerators corporate_fare Google place Sunnyvale, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience. 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.). Experience with RTL design using Verilog or SystemVerilog.

Preferred qualifications:

Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture. Experience interacting with software, architecture, and other cross-functional teams. Experience with a scripting language (e.g., Python or Perl) Experience applying engineering best practices (e.g., code review, testing, refactoring). Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms. Knowledge of high performance and low power design techniques. About the job The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about . Responsibilities Understand the overall application of the chip, proposing and developing improvements in overall design. Design and document one or more blocks of an ASIC, including functionality and timing. Work with software teams on functionality, interfaces, and documentation.