Vice President Security Engineering

Vice President Security Engineering Campbell, CA Job Details $260,000 - $310,000 a year 16 hours ago Qualifications Customer communication Strategic management Security analysis Computer Science Bachelor's degree in electrical engineering Security engineering Engineering Data structures VHDL Scalable systems Electrical engineering 8 years Verilog Team development Analysis skills C++ SoC Bachelor's degree Doctor of Philosophy Team management Master of Science Algorithm design Mentoring Scalability System architecture design Regression testing Product strategy Linux Benchmarking Senior level Electrical Engineering Cross-functional collaboration Multithreading Bachelor's degree in computer science Research & development Communication skills Debugging Cross-functional communication Senior leadership

Full Job Description Vice President of Security Solutions Engineering Location:

Campell, CA Arteris connects innovation. Our technology helps the world's most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow. What You'll Do as a Vice President of Security Solutions Engineering at Arteris Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. The Vice President of Engineering for Security Solutions operates as a core member of the company's senior leadership team, translating business objectives into executable engineering plans, establishing scalable operating mechanisms, and ensures that engineering commitments are credible, visible, and reliably delivered. Reporting to the senior VP of engineering, this leader builds and scales teams, mentoring leaders, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and managed decisively and aligns strategy across the organization. This role will lead a small growing team consisting of both individual contributors and one or more managers. Key Responsibilities Technical Strategy & Architecture Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality. Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs. Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness. Execution & Delivery Own delivery outcomes for software products, including correctness, runtime performance, memory footprint, and scalability. Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems. Drive predictable execution from research through productization in a commercial EDA environment. Balance exploratory research with disciplined engineering practices. Organization & Talent Build, mentor, and retain a strong organization of senior engineers, architects, and engineering managers. Foster a culture of technical excellence, peer review, and evidence‑based decision making. Develop future technical leaders within a mixed research and development engineering organization. Cross‑Functional Leadership Partner with management to translate customer direction and requests into an actionable R D roadmap. Serve as the senior engineering interface to executive leadership on deep technical risks, tradeoffs, and investments. Communicate complex algorithmic issues clearly to non‑specialist stakeholders. What You Bring At least 8 years of experience managing software teams (individual contributors and managers) that build and deliver complex C++ commercial technical applications. Demonstrated history of technical leadership involving setting product direction while also owning software (product) delivery and their outcomes (quality, timelines, reliability, user experience). Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms. Strong grounding in algorithms and data structures for digital logic analysis and transformation Practical understanding of SoC design and verification flows and how EDA tools are used in production environments Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs. Executive-level communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers. Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics. Expert programming and debug skills in modern C++. Proficiency working in Linux. Ability to build, lead, and mentor senior technical leaders (architects, principal engineers, engineering managers) while remaining deeply engaged in architectural and algorithmic design. Must exhibit a collaborative management style while maintaining strong communication and cross-functional leadership. Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities. This position can be based in Campell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings. Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products. Familiarity with hardware security analysis or security oriented verification tools Understanding of RTL/gate-level simulation and debugging. Experience in the implementation and verification of SoC designs. Education Requirements Bachelor's degree in Computer Science or Electrical Engineering (MS/PhD preferred).

Estimated Base Salary:

$260,000 to $310,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. About Arteris Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com. With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.