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Senior/Principal Engineer GPU Modeling / GPU Architect
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MediaTek Inc.
San Diego, CA (In Person)
$232,500 Salary, Full-Time
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Job Description
Senior/Principal Engineer - GPU Modeling / GPU Architect Apply Save Job Category Chip Design Location San Diego, CA Experience More than 8 Years Work Expe. Job Description MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems-on-chip (SoC) for mobile devices, home entertainment, connectivity and IoT products. MediaTek is the number one Wi Fi supplier across broadband, retail routers, consumer electronics devices and gaming, and its Wi Fi 6 chipsets are powering the latest networking equipment for faster computing experiences. Our dedication to innovation has positioned us as a driving market force in several key technology areas, including highly power efficient mobile technologies, automotive solutions and a broad range of advanced multimedia products such as smartphones, tablets, digital televisions, 5G, Voice Assistant Devices (VAD) and wearables. MediaTek empowers and inspires people to expand their horizons and achieve their goals through smart technology, more easily and efficiently than ever before. We work with the brands you know and trust to make great technology accessible to everyone.
- Define and develop best in class GPU architecture and performance/power models for next generation MediaTek SoCs.
- Build and maintain cycle accurate / performance / functional models of GPU subsystems (e.g., shader cores, fixed function units, memory hierarchy, interconnect).
- Use modeling and profiling to explore architectural trade offs (performance, power, area) and guide micro architecture decisions.
- Analyze workloads (games, graphics benchmarks, GPU compute, AI/ML kernels) using simulation and hardware profiling to identify bottlenecks and optimization opportunities.
- Collaborate closely with RTL, DV, software/driver and performance teams to ensure architectural intent is correctly implemented, verified and tuned.
- Provide architectural input to compiler/driver/runtime teams to maximize utilization of GPU hardware through software optimizations.
- Develop methodologies, tools and automation flows for GPU performance estimation, capacity planning and regression analysis.
- Lead the debug and root cause analysis of performance, power and bandwidth issues observed in models, emulation and silicon.
- Drive cross team technical discussions, present modeling results and architectural proposals, and influence roadmap decisions for next generation GPUs. Main Requirements and Qualifications
- BS/MS or higher in Computer Science, Electrical/Computer Engineering or a closely related field.
- 8+ years of experience in GPU, graphics, high‑performance compute, AI accelerator, or related architecture/modeling areas.
- Deep understanding of modern GPU architecture and pipeline (graphics and/or compute), including shader cores, rasterization, tiling, memory systems and scheduling.
- Strong experience with performance and/or cycle‑accurate modeling, simulation frameworks, or architectural exploration for complex SoCs or accelerators.
- Solid understanding of graphics and compute APIs such as Vulkan, OpenGL, DirectX and/or GPU compute frameworks (e.g., OpenCL, CUDA, Metal).
- Proficiency in at least one modeling or implementation language (e.g., C/C++, SystemC, Python) and familiarity with scripting for data analysis and automation.
- Experience with performance analysis tools, profiling methodologies and workload characterization for games, benchmarks and/or GPU compute workloads.
- Good written and oral communication skills, with the ability to present complex technical topics clearly and drive consensus across teams. Preferred Qualifications (Nice to Have)
- Experience with mobile/low‑power GPU design and power/performance trade‑off analysis.
- Background in compiler, driver, or runtime optimization for GPUs or accelerators.
- Familiarity with ML/AI workloads, DNN operators and their mapping onto GPU or accelerator architectures.
- Experience collaborating with silicon implementation, physical design and DV teams on performance and power sign‑off.