Graphics (GPU) Architectural Modeling Engineer

Do you love crafting elegant solutions to highly sophisticated challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.\\n\\nWe are looking for engineers who are passionate about Architectural Models. You will be responsible for the pre-silicon functional and performance modeling of our industry leading low power GPUs. This includes developing detailed models of the architectural and micro-architectural aspects of various blocks and IPs in the GPU and how they operate within the broader GPU design. As a Graphics (GPU) Architectural Modeling Engineer, you will:\n- Develop architectural models for the development, validation, and verification of graphics processing unit (GPU) design.\n- Write bit-accurate architectural models for hardware/software (HW/SW) co-validation.\n- Write timing-accurate architectural and micro-architectural models for performance validation and correlation.\n- Support GPU hardware and software teams during model and design bring-up.\n- Triage regression failures and debug failures to root cause.\n- Improve modeling infrastructure. Minimum of BS + 3 years of relevant experience.\nExperience in C++ programming.\nExperience with C++ modeling of Computer Architectures.\nExperience with scripting languages Python, Ruby, or Perl. Experience with Advanced Computer Architecture.\nExperience with GP-GPU or Parallel Architectures.\nExperience with Computer Memory Hierarchy.\nExperience with bring-up and debug of complex systems.\nExperience with GPU Graphics Pipeline.\nExperience with performance analysis and debug.\nExperience with HDLs, Verilog, System Verilog or VHDL.\nExperience with turning architectural specifications into executable models.