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Principal SoC Integration Flow Architect - Automation
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MediaTek Inc.
San Jose, CA (In Person)
$248,500 Salary, Full-Time
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Job Description
Principal SoC Integration Flow Architect - Automation Apply Save Job Category Chip Design Location San Jose, CA Experience More than 8 Years Work Expe. Job Description We are seeking a high-caliber Engineer to lead the architectural design and development of a next-generation Top-level Integration Flow. Your mission is to build a highly automated framework—comparable to SoC Compiler—that streamlines the path from IP handoff to full-chip netlist generation.
Key Responsibilities:
Framework Architecture:
Design and implement a scalable SoC assembly framework using Python, Perl, Tcl or C++ to automate connectivity, memory map generation, and clock/reset structures.Metadata Standardization:
Define and leverage metadata standards (e.g., IP-XACT) to enable seamless IP integration and configuration.Tool Development:
Build advanced "SoC Compiler" capabilities, including automated RTL generation, stitch-rule checking (LINT/CDC), and synthesis-ready top-level packaging.Optimization:
Collaborate with Front-End and Physical Design teams to integrate PPA-driven constraints into the automation pipeline.Location:
San Jose, or San Diego, CA Main Requirements and Qualifications- Proven experience in SoC Integration and RTL Design (Verilog/SystemVerilog).
- Expertise in scripting and software engineering (Python/Perl/Tcl) applied to EDA flows.
- Familiarity with industry-standard integration tools and the internal logic of automated SoC compilers Salary range: $211,000 - $286,000 Employee may be eligible for performance bonus, short and long term incentive programs.