Senior Silicon Validation Engineer

Senior Silicon Validation Engineer corporate_fare Google place Mountain View, CA, USA bar_chart Mid Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience developing stress tests, silicon validation frameworks, or related infrastructure. Experience in bench level validation and debug. Experience with lab equipment such as Oscilloscopes, Digital Multimeters (DMM), Logic analyzers etc. Experience programming in C/C++/Assembly. Experience scripting in Python/Perl/Tcl.

Preferred qualifications:

Experience with complex system debug, embedded operating systems, or bare metal programming. Experience executing tests on emulation/field programmable gate array (FPGA) and Silicon platforms. Experience with Joint Test Action Group (JTAG) debuggers (e.g., Lauterbach). Experience with Power management IC validation and Power related validation. Experience with Post Silicon debug. Proficiency in Hardware/Software interface with excellent debugging skills. About the job The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about . Responsibilities Plan, develop, and execute tests to validate hardware IP blocks and integration at the system level. Validate design on pre-silicon and post-silicon platforms. Interface with Software, Architecture, Design, and Design Verification (DV) teams to create test plans. Support silicon debug and field failures.