DMTS Digital Design Engineer / Chip Lead

• Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• Responsibilities
• + •

Chip Architecture & Integration:

• Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP. +

• RTL Design:

• Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration. +

• Timing Closure Leadership:

• Develop and own chip-level timing constraints (SDC), define clock domain crossing strategy, and provide timing budgets per block to the Physical Design engineer. +

• Synthesis:

• Drive logic synthesis (DC / Genus) and guide optimization for PPA targets across all design blocks. +

• IP Management:

• Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination. +

• Tape-Out Ownership:

• Own and drive the tape-out checklist sign-off process, coordinating across Physical Design, Verification, and analog team members to achieve clean handoff to the foundry. +

• Design Documentation:

• Author architecture specifications, block-level design specifications, and interface control documents that serve as the authoritative reference for the team. +

• Follow-On Roadmap:

• Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development.
• Basic Qualifications
• + BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field + 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role + Expert-level proficiency in SystemVerilog RTL design and coding best practices + Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus) + Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug) + Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent) + Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment + Ability to work effectively as a technical lead on a small team — comfortable making decisions with incomplete information and owning the outcomes + Strong written communication skills — this role produces specifications, not just code •Preferred Qualifications•+ Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures) + Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations + Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O + Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters + Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart The US base salary range that Micron Technology estimates it could pay for this full-time position is: $206,000.

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