Required Qualifications:

Bachelor s/Master s degree in Electrical Engineering or related field 5 10 years of experience in RTL design and microarchitecture Strong expertise in RTL design using SystemVerilog/Verilog Microarchitecture development for complex digital systems Performance optimization and pipelining techniques Experience with simulation and debugging tools such as: Synopsys VCS / Cadence Xcelium Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler) Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces) Experience working in ASIC/SoC development environments

Preferred Qualifications:

Experience in one or more domains

CPU, GPU, AI/ML

accelerators, networking, or high-speed data processing Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency) Familiarity with low-power design techniques (clock gating, power domains) Exposure to formal verification or linting tools Experience with

GLS, SDF

annotation, and silicon debug Scripting skills (Python/TCL) for automation Understanding of hardware-software interaction (firmware, drivers)