Signal Processor subsystem across all radar variants (D, D(V), D(MOD)). Participate in efforts to analyze and document the design and functional behavior of legacy signal processor components, including digital processing modules, interface cards, and timing assemblies. Support design recovery and traceability efforts, working from GFI, limited technical data, or harvested hardware. Define and support the development of prototype subassemblies, repair processes, and test capabilities to validate organic sustainment approaches. Develop and validate functional test procedures, signal flow diagrams, and performance benchmarks. Identify critical components at risk due to obsolescence, and support alternate part qualification, reverse engineering, or redesign as necessary. Coordinate with systems engineers, test engineers, and OEM partners to ensure alignment with weapon system interface requirements and mission-critical timing/data processing functionality. Provide technical input to Integrated Technical Data Packages (ITDPs), depot stand-up planning, and operator/maintainer training materials. Ensure test and repair processes comply with NAVSEA and METCAL standards where applicable.
Experience and Skills Experience and Skills Required Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. Minimum of 5+ years of experience. Understanding of digital processing architectures, A/D conversion, timing synchronization, and signal conditioning. Experience with diagnostics, troubleshooting, and repair at the board and component level. Familiarity with tools used for signal integrity analysis, logic analyzers, and boundary scan testing. Proven ability to read, interpret, and reverse-engineer technical data, schematics, and embedded processing logic. Experience developing or reviewing test procedures and technical documentation for government sustainment programs. Able to obtain a
Secret Clearance Preferred Qualifications:
Prior work with AEGIS Combat System interfaces, SPY-1 timing architectures, or radar track processing functions. Familiarity with DoD obsolescence mitigation strategies, including reverse engineering, emulation, and form-fit-function redesign. Experience supporting ORDALT implementation, depot activation, or prototype validation. Knowledge of Model-Based Systems Engineering (MBSE) practices or digital engineering toolsets.
Active Seret or TS/SCI Clearance Travel:
~10-20%, including to shipyards, government labs, and partner facilities. #LI-ACI & #LI-Onsite Job Benefits Medical, Dental & Vision Insurance Coverage Life/ADD & Short/Long Term Disability Insurance 401(k) Savings Plan Employee Stock Purchase Plan (ESPP) Paid Time-Off (PTO) Holidays Education Reimbursement group id: 91122198 Apply now
