SOC Engineering, Sr Staff Engineer
Job
SYNOPSYS INC
Austin, TX (In Person)
$196,997 Salary, Full-Time
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Job Description
Between $181k and
$213k
Per Year
Position range in Travis County $90k - $153k Per Year SOC Engineering, Sr Staff Engineer
SYNOPSYS INC
Occupation:
Electronics Engineers, Except ComputerLocation:
AUSTIN, TX - 78746
Job Type:
Regular, Full Time (30 Hours or More), Permanent EmploymentPosted:
04/27/2026 Positions available: 10Source:
WorkInTexasWeb Site:
WorkInTexas Onsite /Remote:
Work onsite all of the timeUpdated:
05/08/2026Expires:
06/15/2026Agency Job ID:
JobID 17431
Job #: 17007233 Job Requirements and Properties Help for Job Requirements and Properties. Work Onsite Full Time Education Bachelor's Degree Experience 72 Month(s) Schedule Full Time Job Type Regular Duration Permanent Employment Public Transit Available Benefits Help for . : Define, design, verify, and create documentation for ASIC development. Perform pre-silicon Verification, including Universal Verification Methodology, Coverage Analysis, Verification plan creation, and debugging. Write C/Assembly tests for SoC verification. Debug RTL and GLS failures. Analyze and enhance protocols, including Peripheral Component Interconnect Express, Universal Chiplet Interconnect Express, Ethernet, Universal Serial Bus, Double Data Rate, and/or process/interconnect/debug architecture. Enhance and utilize verification tools such as VCS, Waveform analyzer, and third-party VIP Integration (such as Synopsys VIPs). 40 hours per week.Job Requirements:
Requires a Bachelors degree or foreign equivalent degree in Computer Science, Electrical/Electronic Engineering, Computer Engineering, or a related field and six (6) years of progressive and post-baccalaureate experience in SOC and design verification. (Alternative education & experience requirements: Master's degree or foreign equivalent degree in Computer Science, Electrical/Electronic Engineering, Computer Engineering, or a related field and four (4) years of experience in SOC and design verification.) Also requires background in: 1) UVM/OVM, System Verilog, Verilog; 2) VCS, Verdi; 3) Linux; 4) Pre-Silicon Verification Planning; 5) Design and Implementation of System Verilog/UVM Testbenches; 6) Defining strategy and developing test plans; 7) Integrating verification collateral; and 8) Coverage analysis and debug.Pay Range and Benefits Information:
The base salary range across the U.S. for this role is between $180,993.66 to $213,000 per year. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Synopsys can share more specific details on the total rewards package upon request. Synopsys is committed to fostering an inclusive and diverse workplace. Synopsys considers qualified applicants for employment without regards to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. To apply, send resume to printads@synopsys.com indicating JobID 17431
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