DFT Engineer JNL Technologies Santa Clara, CA Job Details Full-time $70,000 - $120,000 a year 19 hours ago Benefits Relocation assistance Qualifications Verification (System development task) FPGA Process improvement Electrical engineering Electronics test specifications Digital circuit design Attention to detail Full Job Description Job Summary We are seeking a highly motivated and detail-oriented DFT (Design for Testability) Engineer to join our innovative engineering team. In this role, you will be instrumental in designing, implementing, and optimizing test strategies for complex electronic systems, ensuring seamless manufacturing and reliable product performance. Your expertise will help streamline testing processes, improve yield, and facilitate efficient debugging across a variety of cutting-edge projects involving FPGA, SoC, PCB design, and electrical systems. This position offers an exciting opportunity to contribute to the development of advanced electronics and automation solutions in a dynamic environment. Required Skills Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and

MBIST MBIST

Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG (IEEE 1687) standard and good understanding of ICL and PDL specifications Verification of DFT features, Required Skills Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and

MBIST MBIST

Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG (IEEE 1687) standard and good understanding of ICL and PDL specifications Verification of DFT features,

Including:

Boundary Scan

JTAG SCAN MBIST

High-Speed I/O Boundary Scan

JTAG SCAN MBIST

High-Speed I/O Pay:

$70,000.00 - $120,000.00 per year

Benefits:

Relocation assistance

Work Location:

In person