Meta is seeking a Staff PCB Layout Engineer to drive the design and delivery of complex printed circuit boards for large-scale infrastructure hardware. In this role, you will define layout architecture and establish engineering standards for high-speed digital, power delivery, and signal integrity-critical designs that power Meta's data center and infrastructure platforms. You will partner with electrical engineers, mechanical engineers, and manufacturing teams to shape board-level design strategy from concept through mass production, ensuring reliability and performance at scale.

Qualifications:

8+ years of experience in PCB layout design for high-speed digital systems, including boards with DDR, PCIe, or high-speed SerDes interfaces 8+ years of experience with industry-standard EDA layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent Experience defining PCB stack-up configurations, impedance control strategies, and design rule constraints for high-layer-count boards Experience collaborating with signal integrity and power integrity teams to translate simulation results into layout implementation decisions Experience leading PCB layout efforts across the full product development lifecycle from schematic capture through manufacturing release Experience designing PCBs for data center infrastructure hardware including server, storage, or networking platforms Experience with high-speed (100Gbps+) signal interfaces Experience establishing layout centers of excellence or defining team-wide PCB design standards across multiple concurrent programs Experience with complex designs using custom ASICs