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Principal Signal Integrity & Hardware Systems Engineer (PCIe Gen
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Scout Marketplace - Marvell Semiconductor
Santa Clara, CA (In Person)
$200,000 Salary, Full-Time
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Job Description
Job Title:
Principal Signal Integrity & Hardware Systems Engineer (PCIe Gen5/6)Location:
Santa Clara, CACompensation:
$150K - $250K base DOE plus bonus andRSUsRequirements:
Signal Integrity, PCIe (Gen5/6), High-Speed SerDes, PCB Design, Power Integrity (PI) Analysis, Sigrity / Ansys HFSS, Reference Board Design, EM Modeling & SimulationPosition OverviewWe are seeking an experienced Principal Signal Integrity & Hardware Systems Engineer to lead design and verification of high-performance digital hardware with a focus on PCIe Gen5/Gen6 and 25Gbps+ SerDes interfaces. The role combines advanced signal and power integrity analysis, reference board and PCB design guidance, EM/field simulation, and hands-on lab validation to ensure robust system-level performance. You will drive architecture decisions, mentor engineers, and collaborate across cross-functional teams to deliver scalable, manufacturable solutions for next-generation products.Key ResponsibilitiesLead signal integrity (SI) and hardware systems engineering efforts for PCIe Gen5/Gen6 and other high-speed SerDes interfaces, driving architecture choices, budgeting, and tradeoffs.
Own reference board and PCB design best practices: define stackups, routing topologies, connector/cable interfaces, and layout constraints for high-speed channels.
Perform detailed SI and PI analysis using tools such as Cadence Sigrity, SIsoft, Ansys HFSS, and other EM solvers to model channel loss, crosstalk, reflections, and package effects.
Develop and run channel and link-level simulations (IBIS-AMI, eye, BER, jitter/power-aware analyses) to validate compliance with PCIe and other protocol margins.
Lead power integrity (PI) analysis and decoupling strategies to minimize supply noise impact on SerDes and system timing.
Create EM models of packages, connectors, and PCBs, and use them to inform design changes to improve signal fidelity and EMC performance.
Plan and execute lab validation: setup and run TDR/TDT, VNA, high-speed oscilloscope, BERT, and related measurements for debug and release verification.
Collaborate closely with board layout teams, package engineers, firmware, system architects, and manufacturing to resolve signal and hardware issues from pre-silicon through production.
Mentor and coach other engineers, establish SI/PI processes and checklists, and drive knowledge sharing across the organization.
Support supplier and partner engagements, including reviewing third-party PCB stackups, evaluating test fixtures, and providing technical direction for prototypes and NPI runs.
QualificationsBachelors or Masters degree in Electrical Engineering or related field; PhD preferred but not required.5+ years of hands-on experience in signal integrity, hardware systems, and high-speed digital design with demonstrated leadership on complex products.
Proven experience designing and validating PCIe Gen5 and/or Gen6 links and related SerDes interfaces (protocol compliance and link margining).Strong PCB and reference board design background, including stackup definition, controlled impedance routing, and connector/cable integration.
Proficiency with SI/PI and EM tools such as Cadence Sigrity, SiSoft, Ansys HFSS, Keysight ADS, or similar simulation suites.
Expertise in
IBIS-AMI
modeling, channel simulation, BER/eye analysis, and jitter decomposition techniques.Experience with power integrity analysis and decoupling strategies for high-speed digital systems.
Hands-on lab experience with high-speed test equipment (oscilloscopes, VNAs, TDRs, BERTs) and troubleshooting methodologies.
Experience with EM/package modeling, signal/power co-simulation, and thermal/EM-aware system trade-offs.
Strong scripting and data-analysis skills (Python, MATLAB, or similar) to automate simulations and post-process results.
Excellent communication and cross-functional collaboration skills; experience mentoring engineers and defining engineering processes.
Ability to manage multiple projects, prioritize technical risks, and deliver to schedule in a fast-paced environment.
BenefitsComprehensive medical, dental, and vision plansLife insurance and disability plan options401(k)RSUsESPPPaid company-selected holidays & floating holidaysPTO - generous time off programsCareer growth opportunities