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Job Description Senior Test Lead - Silicon Platform Validation Santa Clara, California Job Summary Work on FPGA prototyping platforms using Synopsys HAPS . The primary goal is to map portions of ASIC designs onto multiple FPGAs to enable early software development and validation before silicon availability Key Responsibilities The FPGA prototyping team is seeking onsite Mountain View engineers with strong Verilog, FPGA debugging, synthesis, timing closure, and lab-debug skills to support a Synopsys HAPS-based prototyping environment. The work centres on multi-FPGA partitioning, RTL adaptation, software bring-up, and independent debugging. Skill Requirements Mandatory Skills Based on the discussion, the following were identified as required skills: Strong Verilog coding and debugging capability. Ability to perform FPGA debugging independently without constant supervision.

Experience with HDL development/debug tools:

Verdi VCS Ability to analyse and debug: UART logs Logic analyser traces Hardware/software integration issues Familiarity with laboratory equipment: Oscilloscope Logic analyser Bus analysers Strong problem-solving and root-cause debugging skills. Good communication skills and ability to follow directions. Willingness to work onsite at Mountain View . Preferred Skills These were discussed as "good-to-have" rather than strict requirements: Prior experience with Synopsys

HAPS FPGA

prototyping platform . FPGA synthesis and implementation experience. Multi-FPGA partitioning knowledge using ProtoCompiler or similar FPGA compilation flows. Timing closure and FPGA optimisation experience. Experience creating specialised debug builds and exposing internal signals for debug. Understanding of FPGA-based hardware bring-up and software boot flows. Other Requirements Smart, capable engineers are preferred over purely experience-based hiring decisions. Experience is beneficial but not the primary selection criterion. Maximum Salary (US): 148000 Minimum Salary (US): 78000 Apply now Job Alerts Link