Skip to main content
Tallo logoTallo logo
Apply for this opportunity

This job application is on an outside website. Be sure to review the job posting there to verify it's the same.

Advanced FPGA & ASIC Engineer with strong RTL (Verilog/SystemVerilog)

Job

Revolution Technologies, LLC

Minneapolis, MN (In Person)

$178,880 Salary, Full-Time

Posted 3 weeks ago (Updated 1 week ago) • Actively hiring

Expires 7/12/2026

Review key factors to help you decide if the role fits your goals.
Pay Growth
?
out of 5
Not enough data
Not enough info to score pay or growth
Job Security
?
out of 5
Not enough data
Calculating job security score...
Total Score
80
out of 100
Average of individual scores

Were these scores useful?

Skill Insights

Compare your current skills to what this opportunity needs—we'll show you what you already have and what could strengthen your application.

Job Description

We are hiring an Advanced
FPGA & ASIC
Engineer with strong RTL (Verilog/SystemVerilog) experience to support high-performance hardware development. About the Company Our client is a leading provider of advanced engineering solutions supporting mission-critical programs across defense, aerospace, and high-performance computing environments. Their teams focus on developing cutting-edge hardware and integrated systems for complex, high-reliability applications. The organization is known for delivering challenging, hands-on engineering work and partnering with top-tier technical teams across the full system lifecycle. About the Role This is a 12-month contract with strong potential for extension. Responsibilities Design, develop, and verify both FPGA and ASIC solutions Define architecture and requirements Perform RTL design and simulation (Verilog/SystemVerilog) Execute synthesis, place & route, and timing analysis Support system integration, validation, and testing Support FPGA prototyping and hardware validation of ASIC designs Develop and execute simulation and test plans Collaborate across hardware, software, and systems engineering teams Evaluate performance, power, and scalability tradeoffs Contribute to continuous improvement of design methodologies and processes Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's preferred) Hands-on experience in BOTH FPGA and ASIC design across the full development lifecycle Required Skills Strong expertise in: RTL design (Verilog/SystemVerilog) FPGA development and debugging ASIC design flows (e.g., synthesis, timing, validation) Experience with tools such as Vivado, QuestaSim, or similar Solid understanding of digital design, timing analysis, and hardware optimization Experience working in hardware-centric environments (not software-only roles) Preferred Skills ASIC tapeout or silicon validation FPGA prototyping to support ASIC development High-speed interfaces (SERDES, SPI, I2C, AXI) Background in defense, aerospace, or high-reliability systems Experience working in cross-functional engineering teams
Duration:
12-month contract (likely extension)
Schedule:
Full-time, onsite
Start:
ASAP If you have strong experience in both FPGA and ASIC design and enjoy solving complex hardware challenges across the full development lifecycle, we encourage you to apply.
Key Skills:
FPGA ASIC RTL
Design Verilog SystemVerilog Digital Design Hardware Engineering FPGA Development ASIC Design VHDL (optional but helpful)
Embedded Systems Pay:
$82.00 - $90.00 per hour
Benefits:
Dental insurance Health insurance Vision insurance
Work Location:
In person