ASIC/FPGA Design Engineer (SMES)

Location:

Gloucester City, NJ Salary:

$70.00 USD Hourly - $80.00

USD Hourly Description:

Our client is currently seeking a

ASIC/FPGA

Design Engineer (SMES).

Essential Functions:

Responsible for deriving engineering specifications from system requirements and developing detailed architecture Execute design (RTL

AND/OR HLS

(C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) Generate test plans Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards Silicon/FPGA bring up, characterization and production ramp/support/collateral

Qualifications:

BSEE, MSEE

Preferred. 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking

ASIC/FPGA

products. Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs. Proficient with

CDC, RDC.

Formal EDA. Proficient in VHDL. Proficient with

Synthesis/PAR:

SDC, Synopsys Synplify, Vivado Strong logic/board debug, and analytical skills. Experience with project leadership and EVM Excellent written, verbal, and presentation skills.

Active SECRET Clearance Preferred Additional Skills:

A big plus if the candidate possesses "any" of the following: Proficiency in C++ (OOP) Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS. Knowledge of PCIe, NVMe, USB protocols. Experience with High level synthesis (Xilinx Vivado

HLS, AND/OR

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Contact:

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