Job Listing ID:

4571689

Job Title:

Signal Integrity Lead

Application Deadline:

10/17/2026

Job Location:

Hillsboro

Date Posted:

09/18/2026

Hours Worked Per Week:

40

Shift:

Day Shift

Duration of Job:

Full Time, more than 6 months

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Job Summary

Key Responsibilities Own end-to-end SI analysis and design closure for PCIe Gen 6+ and CXL interfaces from early architecture through platform validation. Develop channel budgets, margin analyses, design rules, signoff criteria, and correlation plans for PCIe/CXL links. Own SI architecture and technical guidance for PCIe REFCLK distribution, including jitter-budget and topology considerations. Own SI analysis and integration guidance for retimers and redrivers, including placement, channel partitioning, model use, and system margin. Build and maintain package-to-board and full-channel simulation models using frequency-domain and time-domain methods, including S-parameter and

IBIS-AMI

based analysis as applicable. Provide actionable guidance for PCB stackups, materials, routing constraints, via transitions, connectors, cables, and component selection within the PCIe/CXL domain. Assess die/package SI inputs and package-to-board interactions for PCIe/CXL, working with silicon and package teams and providing recommendations to the SI Lead for platform integration and signoff. Define PCIe/CXL validation and platform-compliance-evidence methodology; partner with the validation engineer on measurement execution, lab correlation, margin demonstration, and debug. Partner with firmware, system, and component teams on link bring-up, equalization, retimer firmware interactions, interoperability, and root-cause analysis. Develop and automate analysis flows to improve productivity, accuracy, repeatability, and scalability. Contribute interface-specific content to design guides, customer collateral, technical reviews, and recommendations for engineering teams, senior leadership, customers, suppliers, and ODM partners. Mentor engineers and provide technical direction within the PCIe/CXL area of ownership. Qualifications Master's degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems. Demonstrated ownership of PCIe interface SI from architecture and specification through system validation; PCIe Gen 6 or comparable high-speed SerDes experience strongly preferred. Strong knowledge of transmission-line theory, channel analysis, insertion and return loss, crosstalk, S-parameters, jitter, equalization, link margin, and system-level optimization. Experience with PCIe/CXL channel modeling, compliance methodology, REFCLK analysis, and retimer/redriver integration. Hands-on experience creating package-to-board and full-channel models and performing frequency-domain and time-domain simulations. Proficiency with one or more relevant simulation environments, such as ANSYS HFSS/SIwave, Cadence Sigrity/Clarity, Dassault Systemes CST, Keysight ADS, or Synopsys HSPICE. Experience with electrical validation and correlation using oscilloscopes, VNAs, TDR systems, BERTs, protocol analyzers, traffic generators, or related laboratory equipment. Proficiency in Unix/Linux environments and scripting for EDA workflow automation. Strong understanding of package and PCB technologies, design methodology, and manufac Electronics Engineers, Except Computer

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Compensation

$221,100.00 to $331,700.00 per Year

Job Requirements

Experience Required:

At least 8 years

Education Required:

None

Minimum Age:

N/A