Responsibilities:

Required Skills and Experience:

Experience of designing complex, impedance controlled multi-layer (>20), conventional and HDI PCBs with very high pin count devices (>2000), high-speed interfaces (PCIe and DDR), differential pairs, including accommodating high-current PDNs Experience of collaborating with a chip packaging team. Able to advise on pinout and routing topologies of high-density SoCs, cost optimisation and layer trade-off analysis Detailed knowledge of escape routing of high density SoC's, FPGAs, able to provide estimates of the IO count that can be routed with a particular stack-up and rule set Appreciation of Signal Integrity and Power Integrity as applicable to routing strategies Extensive knowledge of the PCB fabrication process (conventional and sequential), IPC standards and stackup topologies, substrate materials, via structures and design rules Proficient in the use of EDA Tools, specifically Cadence OrCAD CIS and Allegro PCB Ability to collaborate with PCB fabricators and CEMs for DFM/DFT and automated assembly. Ensure designs are aligned with supplier capabilities and best practise Good interpersonal skills. Participate in reviews, providing advice to engineers relating to design rules, PCB fabrication and substrate technologies "Nice To Have"

Skills and Experience:

Certified Interconnect Designer (CID, CID+) Experience with schematic entry for symbol and creation and updates from design reviews Experience of automating: decoupling capacitor optimisation, IC placement optimisation, templates etc.

In Return:

Salary Range:

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