IC Layout Engineer Rise Technical Recruitment Limited - 4.0 Plano, TX Job Details Full-time $110,000 - $130,000 a year 1 day ago Benefits Stock options Health insurance Qualifications KiCad Verification (System development task) Integrated circuits (ICs) Technical documentation Grounding systems Collaboration with manufacturing teams Senior level Semiconductor experience Cross-functional communication Full Job Description IC Layout Engineer / Semiconductor Layout Engineer $110,000 - $130,000

+ Stock Options

+ Health Benefits + 401(k)

+ Technical Training & Development

+ Cutting-Edge Space Semiconductor Tech On-site role in Plano, Texas (Dallas-Fort Worth area) Are you an IC Layout Engineer or Semiconductor Layout Engineer looking for a role where you can own full-chip layouts through tapeout, keep learning in a fast-moving environment, and work on cutting-edge technology built for spacecrafts and satellites? On offer is a secure, permanent position with a growing specialist semiconductor business that invests in technical development and gives you real ownership across the layout lifecycle. This is a fabless team known for innovative radiation-hardened ICs used on spacecrafts. As a result of continued growth and ongoing contracts, they are now adding to their layout function. In this role you will lead floorplanning from chip boundary down to leaf-cell level, build and maintain power/ground grids, implement ESD structures, support standard-cell library work, and run LVS/DRC using industry tools, while partnering with design, project owners, and foundry stakeholders. This role would suit a Layout Engineer with strong analog/digital layout fundamentals looking for high-impact ownership, continuous technical development, and the chance to work on advanced ICs for demanding environments.

The Role:

Own full-chip IC layout from floorplan through tapeout (.gds/.oasis) Power/ground grid development, routing/channel planning, EMIR/voltage-drop considerations, and ECO-friendly "future-proofing" ESD cell implementation, documentation of verification flows, and weekly layout status updates Cross-functional collaboration with design engineering, project owners, foundry, and (as needed) external contractors Full-time, on-site position based in

Plano, Texas The Person:

IC/semiconductor layout experience across modern process nodes Experience with LVS/DRC verification and layout tools (Cadence and/or similar; PVS/Assura/Calibre; KiCad) Strong understanding of layout integrity topics (ESD, latch-up, antenna, cross-talk/coupling, EMIR mitigation)

Reference Number:

BBBH280653

Rise Technical Recruitment Inc of 1011 Centre Rd, Suite 322, Wilmington, DE 19805 act as an employer-paid private personnel agency. The salary advertised is the bracket available for this position. The actual salary paid will be dependent on your level of experience, qualifications and skill set and will be decided by our client, the employer. Rise are not responsible or liable for any hiring decisions made by the end client. We are an equal opportunities company and welcome applications from all suitable candidates.